1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device provided with Double Diffused Metal Oxide Semiconductor (which will be referred to as “DMOS” hereinafter) transistors and others.
2. Description of the Background Art
A semiconductor device provided with the DMOS transistors will be described below as an example of the semiconductor device for switching a large current. As shown in FIG. 31, an N−-type epitaxial layer 102 is formed on a p-type silicon substrate 101. N+-type diffusion regions 106a-106d are formed at and near the surface of N-type epitaxial layer 102. A P-type diffusion region 105a surrounding N+-type diffusion regions 106a and 106b is formed at and near the surface of N−-type epitaxial layer 102. Likewise, a P-type diffusion region 105b surrounding N+-type diffusion regions 106c and 106d is formed.
A gate electrode portion 108a is formed on the surface of P-type diffusion region 105a, which is located between N+-type diffusion region 106a and N−-type epitaxial layer 102, with an insulating film therebetween. A gate electrode portion 108b is formed on the surface of P-type diffusion region 105b, which is located between N+-type diffusion region 106c and N-type epitaxial layer 102, and the surface of P-type diffusion region 105a, which is located between N+-type diffusion region 106b and N−-type epitaxial layer 102, with an insulating film therebetween.
A source electrode portion 109 is electrically connected to N+-type diffusion regions 106a-106d. A field isolating film 114 is formed at the surface of N−-type epitaxial layer 102. A drain electrode 110 is formed on a side of field isolating film 114 remote from gate electrode portion 108a. 
Drain electrode 110 is electrically connected to N+-type diffusion layer 104 formed at N−-type epitaxial layer 102. An N+ embedded diffusion region 103 is formed between p-type silicon substrate 101 and N−-type epitaxial layer 102. A p-type diffusion region 107 is formed under field insulating film 114.
An operation of the semiconductor device described above is as follows. By applying a predetermined potential to gate electrode portions 108a and 108b, channel regions are formed in P-type diffusion regions 105a and 105b, and a current flows from source electrode portion 109 through N+-type diffusion regions 106a, 106b and 106c to drain electrode portion 110 as indicated by arrows.
In the above operation, as shown in FIG. 32, a depletion layer (depletion layer A) expands from the interfaces between N−-type epitaxial layer 102 and P-type diffusion regions 105a and 105b toward N−-type epitaxial layer 102. Likewise, a depletion layer 120 (depletion layer B) expands from the interface between P-type diffusion region 107 and N−-type epitaxial layer 102 toward N−-type epitaxial layer 102. In particular, depletion layer B suppresses concentration of an electric field, and durability is improved. The conventional semiconductor device provided with the DMOS transistors has the foregoing structure, and operates in the foregoing manner.
As described above, P-type diffusion region 107 is formed for the purpose of suppressing the concentration of the electric field by the depletion layer which extends from the interface between P-type diffusion region 107 and N—type epitaxial layer 102 toward the N−-type epitaxial layer 102, and thereby improving the breakdown voltage. However, in the on state where a current flows from source electrode portion 109 toward drain electrode portion 110, such a problem occurs that P-type diffusion region 107 intercepts the current flow so that the on resistance rises.
FIG. 33A is a graph showing a result of evaluation of a relationship between the drain current and the drain voltage with various gate voltages of the DMOS transistor, which is not provided with P-type diffusion region 107. FIG. 33B is a graph showing a result of evaluation of the relationship between the drain current and the drain voltage in the DMOS transistor provided with P-type diffusion region 107.
As shown in FIGS. 33A and 33B, the drain current in the structure provided with P-type diffusion region 107 is lower than that in the structure not provided with P-type diffusion region 107 if the same drain voltages are used. In particular, when the drain voltage is relatively low, the drain current is likewise low.
Therefore, the structure provided with P-type diffusion region 107 suffers from such a problem that the on resistance in the on state is approximately three-five times larger than that in the structure not provided with P-type diffusion region 107.